The development of computer graphics system creates the need for fast memories capable of storing huge amounts of data, such as 3-D graphics data. Among such memories are cached memories developed to improve DRAM main memory performance by utilizing a faster SRAM cache memory. For example, U.S. Pat. No. 5,566,318 discloses an enhanced DRAM that integrates a SRAM cache memory with a DRAM on a single chip. Sense amplifiers and column write select registers are coupled between the SRAM cache and the DRAM memory array. A column decoder is associated with the SRAM cache for providing access to the desired column of the SRAM. A row decoder is associated with the DRAM memory array to enable access to particular rows of the DRAM. Input/output control and data latches receive data from the SRAM to provide data output via data input/output lines. The current row of data being accessed from the DRAM memory array is held in the SRAM cache memory. Should a cache "miss" be detected, the entire cache memory is refilled from the DRAM memory array over a DRAM-to-cache memory bus.
The speed of data reading and writing in a RAM is limited due to switching delays between the moment the RAM is activated and the instant valid data appear at the input or output. For example, a DRAM read operation may be activated by switching the row address strobe /RAS and the column address strobe /CAS to a low level. For example, the delay in data reading is determined by the RAS latency that corresponds to the delay between the instant the /RAS signal goes low and the moment valid data appear at the output.
It would be desirable to provide independent concurrent DRAM and SRAM operations, in order to continue SRAM writing or reading operations after a DRAM operation is activated. This would increase the bandwidth of data transfer in the RAM by eliminating RAM switching delays caused by the RAS latency.
In synchronous memories, a chip select signal /CS is used to disable the internal clock when the current command should be ignored, for example in a No Operation (NOP) mode. As illustrated in FIG. 1, for supporting input or output of data DQ, a synchronous memory may use such input command signals as row and column address strobes /RAS and /CAS, write enable command /WE, or an operation control signal /DSF. The chip select signal /CS is supplied at the rising edge of the system clock CLK to validate or invalidate the input command signals produced at the same rising edge of the system clock.
For example as shown in FIG. 1, the chip select signal /CS set at a high level (/CS=H) may indicate that the corresponding input command signal should be ignored. In this case, the internal clock of the synchronous memory (Internal CLK) to be produced in the next system clock cycle is disabled. As a result, the corresponding input command is not executed. When the chip select signal /CS is set at a low level (/CS=L), the internal clock is produced to support an operation defined by the corresponding input command.
However, a single chip select signal cannot support independent operations of SRAM and DRAM arranged on the same chip. Therefore, it would be desirable to provide a chip select system that allows a user to perform SRAM and DRAM operations independently.
Moreover, in a graphics subsystem, multiple memory chips connected in parallel are required for storing data. In such a multi-chip memory system, each two memory chips may be combined into a memory bank. As all the input command signals are supplied in parallel to every bank in the memory system, a single chip select signal would not allow DRAM and SRAM operations in the memory banks to be performed independently. For example, a DRAM transfer in bank 1 will be initiated in response to a request for a DRAM operation in bank 2.
Therefore, it would be desirable to provide a chip select system that would support independent DRAM and SRAM operations in a multi-chip memory system.